Architectural View and Low Power Technology for PFLOPS Computing

Taisuke Boku

Professor, Department of Computer Science, Graduate School of Systems and Information Engineering, University of Tsukuba

@

<Abstract>

There has been a strong requirement for PFLOPS-class computation resources on wide variety of computational science and engineering problems. It includes not only gCapability Computingh where a very high computation power is required for a single problem but also gCapacity Computingh where a large number of computations each of them requires relatively small or medium computation power. As a solution to these demands, MEXT Japan decided to start a national project to build 10 PFLOPS-class system, so called gKEI-SOKUh Computer (gKEIh means 1016 in Japanese counting manner).

Since the target computation power is so huge, it is impossible to configure the system just with a brute force to extend current machines with 10 ? 100 TFLOPS-class performance. Especially, we must solve the problem of the electricity and the space. Either the machine will be used for capability computing or capacity computing, there is a limitation of power consumption as well as the installation space. For example, the Earth Simulator in Japan consumes approximately 7 MW of power to provide 40 TFLOPS of peak performance where the performance/power ratio is 5.7 MFLOPS/W. With just a simple extension of the system, we need 1.75 GW of power, which corresponds to the total electricity of a big city with a million of population, to achieve 10 PFLOPS of performance. The situation is the same also for the space. The Earth Simulatorfs floor occupancy is approximately 1500 m2, the size of a gymnasium. It means that we need 0.38 km2 which corresponds to the size of a town with 2500 families. Of course, these stories are unacceptable and we really need to develop the machine with much harder challenge we have ever experienced.

In this talk I will consider the possible architectural solutions to realize this class of system for the levels of processor, computation node, interconnection network and whole machine. There are several possibilities for the processor such as vector, scalar or special purpose one. The configuration of a node varies from a single CPU to a large scale SMP with hundreds of CPUs. For the selection of interconnection network, single stage crossbar switch, multi-stage crossbar switch, any type of tree (simple or fat-tree) or traditional mesh/torus topology is considerable. These selections are not individual because the size and class of each component strongly relies on other ones. Therefore, we need to consider which combination is the best to reach to the final goal.

We also need a ultra low power technology both on the CPU and the interconnection network to solve the power problem in a practical way. The state of the art CPUs provide good performance/power ratio, but we have to achieve the ratio of 1GFLOPS/W range. One of the solutions is to extend current low power CPU technology for embedded systems to High Performance Computing. There are few researches on low power interconnection compared with that for CPU. I will show some examples and the way to focus on this topic.

In the Center for Computational Sciences, University of Tsukuba, we have been proposing a new type of MPP system to realize KEI-SOKU performance with the practical electricity and the space based on low-power technology both on CPU and network. I will show our idea and conceptual design as one of the solutions to the problem. I also will introduce our related work to construct a unique large scale PC cluster, PACS-CS for computational sciences as well as a specially designed hybrid cluster, FIRST for large scale computational astrophysics.


<Biographical Notes>

Present

Professor, Department of Computer Science, Graduate School of Systems and Information Engineering, University of Tsukuba

Education

1980 - 1983 Undergraduate Student in the Faculty of Electrical Engineering, Keio University, Obtained B.Sc.

1984 - 1985 Graduate Student in the Department of Electrical Engineering, Institute of Engineering, Keio University, Obtained Master Degree (Thesis advisor; Dr. Hideo Aiso)

1986 ? 1991 Graduate Student in the Department of Electrical Engineering, Institute of Science and Technology, Keio University, Obtained Ph.D. (Thesis advisor, Dr. Hideo Aiso)

Academic Career

1988 - 1992 Assistant Professor at Department of Physics, Faculty of Science and Technology, Keio University

1992 - 1995 Lecturer at Institute at the Institute of Electronics and Information Engineering, University of Tsukuba

1995 - 2004 Associate Professor at the Institute of Electronics and Information Engineering, University of Tsukuba

2004 ? 2005 Associate Professor at the Graduate School of Systems and Information Engineering, University of Tsukuba

2005 - Professor at the Graduate School of Systems and Information Engineering, University of Tsukuba

Academic Awards

2003 Journal Paper Award at Information Processing Society Japan (Japan)

2004 Best Paper Award, High Performance Computing Symposium in Information Processing Society Japan (Japan)

2004 Journal Paper Award at Information Processing Society Japan (Japan)


My research area includes the architecture and performance evaluation of parallel processing systems, especially large scale parallel machines for scientific calculations. Ifm interested into@the basic architecture of both interconnection network and node processor. Recent research topics are: trunk of commodity network links to provide very high bandwidth, ultra low-power@processor technology based on processors for embedded systems, hybrid cluster with general@purpose and special purpose processors, grid and P2P middleware for ad-hoc communication@environment, etc.

@